`timescale 1ps / 1ps
module dm(input clk,
          input MemWr,
          input [31:0] Address,
          input [31:0] DataIn,
          output [31:0] DataOut);
    
    reg [31:0] DATA [1023:0];
    assign DataOut = DATA[Address];
    
    always @(posedge clk) begin
        if (MemWr) DATA[Address] = DataIn;
    end
    
endmodule
